Hardware-software co-design of resource constrained systems on a chip”, Distributed Computing Systems Workshops

This paper presents a hardware-software co-design methodology for resource constrained SoC fabricated in a deep submicron pro-cess. The novelty of the methodology consists in contemplat-ing critical hardware and layout aspects during system level de-sign for latency optimization. The effect of interconnect para-sitic and delays is considered for characterizing bus speed and data communication times. The methodology permits coarse and medium grained resource sharing across tasks for execution speed-up through superior usage of hardware. The paper offers experi-ments for the proposed co-design methodology, including a JPEG SoC